• DocumentCode
    2066786
  • Title

    Fine-grain update control protocol for a distributed shared memory system

  • Author

    Al-Khoury, A.N.M. ; Yamazaki, Takeshi ; Yonezawa, Naoki ; Yamagiwa, Shin Ichi ; Kulkasem, Pusit ; Ono, Masaaki ; Wada, Koichi

  • Author_Institution
    Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
  • Volume
    1
  • fYear
    1997
  • fDate
    20-22 Aug 1997
  • Firstpage
    125
  • Abstract
    The paper proposes a new coherence protocol for a distributed shared memory (DSM) system, called the Selective Validity Control (SVC) protocol. There are two main obstacles that degrade the performance of a DSM system as follows: (1) it is difficult to hide access latency efficiently; (2) the excessive amount of unnecessary coherence traffic is generated. The SVC protocol is the coherence protocol that alleviates these problems by introducing fine-grain control of data transfer. The SVC protocol can also promote and improve the effectiveness of the prefetch operation by allowing cache lines to have partially valid/invalid states. The paper discusses the major problems of a conventional DSM system, and describes the design, characteristics, and primitives of the SVC protocol in detail. To evaluate the performance of the SVC protocol, a trace-driven simulator has been developed. Benchmark programs such as Gauss elimination, Fibonacci, FFT, and Jacobi iteration, were executed on the simulator to measure the amount of data transferred and the number of coherent messages issued. The simulation results show that the SVC protocol can maintain the coherence with less traffic and also minimizes the number of messages required compared to the conventional protocols
  • Keywords
    cache storage; distributed memory systems; protocols; shared memory systems; software performance evaluation; virtual machines; FFT; Fibonacci; Gauss elimination; Jacobi iteration; Selective Validity Control protocol; benchmark programs; cache lines; coherence traffic; coherent messages; distributed shared memory system; fine-grain data transfer control; fine-grain update control protocol; partially invalid states; partially valid states; performance degradation; performance evaluation; prefetch operation; trace-driven simulator; Access protocols; Control systems; Degradation; Delay; Gaussian processes; Jacobian matrices; Multicast protocols; Prefetching; Static VAr compensators; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Computers and Signal Processing, 1997. 10 Years PACRIM 1987-1997 - Networking the Pacific Rim. 1997 IEEE Pacific Rim Conference on
  • Conference_Location
    Victoria, BC
  • Print_ISBN
    0-7803-3905-3
  • Type

    conf

  • DOI
    10.1109/PACRIM.1997.619917
  • Filename
    619917