Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits

Two gate-voltage-bias techniques for gate-coupled MOS (gcMOS) electrostatic discharge (ESD) protection circuits are proposed in this paper. The proposed techniques bias the gate voltage of discharging transistor to approximately half of its drain voltage during an ESD event through either subtraction circuit elements or division circuit elements in order to achieve highest second breakdown current (I_t2) levels. Besides, leakage current levels of protection circuits with proposed gate-voltage-bias techniques are verified to be smaller than that of the traditional design.