Design and implementation of HPF IP generator

This work demonstrates the implementation of high-performance visual IP generator for High Pass (HP) filter using Microsoft Visual Studio 2008. The sum of multiple constant coefficient multiplications (MCM) is the major part in the HP filter. In the Visual IP Generator, we proposed a novel algorithm that can translate the sum of coefficient product term on behalf of HP filter into the sum of bit shifted term, and then uses Booth Algorithm as well as operation group reusable to minimize the number of bit shifted term for reducing adder used. The HP filter IP generated from this work is also compiled and simulated in Altera Quartus II and compared with the Altera FIR Compiler synthesized HP filter. The comparison results verified our implemented HP filter is better than the HP filter constructed by Altera FIR Compiler. Our design can be accomplished by three stages: set up HP filter parameters, establish the simplified adder tree using proposed novel algorithm, and synthesis the VHDL Code. Through these steps, user can save a lot of time and effort in designing and simulation a HP filter in VHDL code.