Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing

Adaptive VSS boosting with process variation compensation is proposed to reduce the standby leakage by 6X at room temperature and improves the write static noise margin. The N-pulse read assist circuit enables higher read stability and faster read speed. The systematic BL capacitance variation is detected, and a proper WL voltage is generated to mitigate the BL discharging speed variation by 20%.