A 2Mb ReRAM with two bits error correction codes circuit for high reliability application

A 2-Mb resistive random access memory (ReRAM) is demonstrated in 0.13-um CMOS logic process. The paper describes the cell, chip architecture, and circuit techniques to ReRAM design; The 2-Mb ReRAM chip features three circuit technologies to improve the memory yield and performance: 1) for a better endurance and resistance distribution a ramped current pulse write driver (RCPWD) circuit is designed, 2) considering process variation and verify used, a programmable reference sense amplifier (PRSA) for stable read operation is designed, and 3) for improving the yield and reliability for some special application, a double error correction codes (DEC) circuit is introduced for yield requirement of high reliability applications.