Iterative-Constructive Standard Cell Placer for High Speed and Low Power

Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still compete on the bases of the shorter combined interconnection length. In this paper, we present a standard cell placer that has timing and power minimization as main goals and is substantially superior in this respect to the popular commercial timing-driven placer. Simultaneously, the new placer is at least as good as the commercial placer w/r to the combined interconnection length. The improvement in timing and power is achieved by careful balancing between iterative and constructive parts of the placement procedure implemented by dynamic reevaluation of constraints for the constructive part of the algorithm. The new placer improves timing by 23% on the average, or for the same timing, reduces power by 14% on the average. It runs more than 2 times faster than the commercial tool.