VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder

In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.