DocumentCode :
2067399
Title :
Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs
Author :
Lines, Andrew
Author_Institution :
Fulcrum Microsystems, Calabasas, CA, USA
fYear :
2003
fDate :
20-22 Aug. 2003
Firstpage :
2
Lastpage :
9
Abstract :
Asynchronous circuits can provide an elegant and high performance interconnect solution for synchronous system-on-chip (SoC) designs with multiple clock domains. This ´globally asynchronous, locally synchronous´ (GALS) approach simplifies global timing and synchronization problems, improving performance, reliability, and development time. Fulcrum Microsystems´ SoC interconnect, ´Nexus´, includes a 16 port, 36 bit asynchronous crossbar which connects via asynchronous channels to clock domain converters for each synchronous module. Each synchronous module has its own local clock domain, and can send a variable length burst of data to any other module. In TSMC´s 130 nm LV low-K process, the system achieves 1.35 GHz at 1.2 V with less than 5 mm2 area. Power scales linearly with bandwidth, from a few mW of leakage to 8 W at the peak 780 Gb/s cross-section bandwidth. Latency through the interconnect is 2 ns plus 1/2 to 2/3 clock cycles of the receiving module. This compares favorably with other SoC interconnect solutions that have less bandwidth, higher energy per transfer and longer latencies. Nexus is an innovative and comprehensive solution to the challenge of SoC interconnect.
Keywords :
asynchronous circuits; clocks; integrated circuit design; integrated circuit interconnections; logic design; pipeline processing; system-on-chip; timing; 1.2 V; 1.35 GHz; 130 nm; 2 ns; 36 bit; 780 Gbit/s; 8 W; GALS; Nexus; asynchronous crossbar interconnect; clock domain converters; globally asynchronous locally synchronous; integrated pipelining; interconnect latency; multiple clock domain SoC; synchronous modules; synchronous system-on-chip design; timing; variable length data burst; Asynchronous circuits; Bandwidth; Chip scale packaging; Clocks; Delay; Integrated circuit interconnections; Power system interconnection; Synchronization; System-on-a-chip; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Interconnects, 2003. Proceedings. 11th Symposium on
Print_ISBN :
0-7695-2012-X
Type :
conf
DOI :
10.1109/CONECT.2003.1231470
Filename :
1231470
Link To Document :
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