DocumentCode :
2067529
Title :
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
Author :
Ooi, Chia Yee ; Fujiwara, Hideo
Author_Institution :
Nara Inst. of Sci. & Technol., Nara
fYear :
2007
fDate :
1-4 Oct. 2007
Firstpage :
425
Lastpage :
431
Abstract :
This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
Keywords :
logic testing; sequential circuits; acyclic sequential circuits; acyclic test generation complexity; design-for-test method; partial scan method; test generation procedure; Circuit testing; Cities and towns; Combinational circuits; Design for testability; Design methodology; Information science; Paper technology; Registers; Sequential analysis; Sequential circuits; Acyclic test generation; design-for-test; sequential circuits; test generation complexity;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2006. ICCD 2006. International Conference on
Conference_Location :
San Jose, CA
ISSN :
1063-6404
Print_ISBN :
978-0-7803-9707-1
Electronic_ISBN :
1063-6404
Type :
conf
DOI :
10.1109/ICCD.2006.4380851
Filename :
4380851
Link To Document :
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