A dual-level matching algorithm for 3-stage Clos-network packet switches

Author

Chao, H. Jonathan ; Liew, Soung Y. ; Jing, Zhigang

Author_Institution

Polytech. Univ. Brooklyn, New York, NY, USA

fYear

2003

fDate

20-22 Aug. 2003

Firstpage

38

Lastpage

43

Abstract

In this paper, we present a new dual-level matching algorithm for 3-stage Clos-network packet switches, called d-MAC. Using a two-level matching algorithm, namely module-level matching and port-level matching, d-MAC is highly scalable and maintains high system performance. The module-level matching is responsible for finding the module-to-module matching according to the queue status of the switch, while the port-level matching is responsible for determining port-to-port matching and route assignment simultaneously. The two-level matchings are computed in a pipelined and parallel manner to speed up packet scheduling.

Keywords

multistage interconnection networks; packet switching; scheduling; telecommunication network routing; d-MAC; dual-level matching algorithm; module-level matching; packet switching; packet-scheduling scheme; parallel architecture; pipelined architecture; port-level matching; route assignment; routers; switch queue status; tri-stage Clos-network packet switches; Chaos; Fabrics; Internet; Packet switching; Round robin; Routing; Scheduling algorithm; Switches; System performance; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Interconnects, 2003. Proceedings. 11th Symposium on

Print_ISBN

0-7695-2012-X

Type

conf

DOI

10.1109/CONECT.2003.1231475

Filename

1231475