Interleaved dual tag directory scheme for cache coherence

Shared memory multiprocessors generally use caches to improve the performance. This introduces the cache coherence problem. Multiple copies of the data need to be kept consistent by using a suitable mechanism. The paper presents a novel mechanism for organizing the memory modules in order to provide an inexpensive implementation for cache coherence. The interleaved directory scheme uses a unique address mapping to ensure a proper distribution of the directory that holds information regarding cached copies in the system. The memory requirement for the directory is significantly less than current directory schemes and there is no extra interconnect traffic generated by the scheme.<>