Characterization of MOS transistor after through-hole electrode fabrication and 3D-assembly by mechanical caulking

Three-dimensional (3D) packaging technology has recently been developed for System in Package applications. The 3D packaging technology with through-hole electrodes has been receiving an especially great deal of attention because through-hole electrodes technology results in compact and high-performance systems. We have developed a new chip-to-chip interconnection method using mechanical caulking with through-hole electrodes and Au stud-bumps. In this method, bonding between chips is achieved by the deformation-injection of an Au stud bump on a chip into a through-hole electrode on the other chip. Therefore, electrical interconnection between stacked chips can be achieved by simply applying a pressing load at room temperature. In this study, the through-hole electrodes were formed from the backside of a wafer by via-last processing. However, fabricating through-hole electrode for existing products such as the micro-controller unit fraught with difficulty because the through-hole electrodes must be connected to external lands (aluminum electrodes for wire bonding) located on the front- side of the wafer. This requires a sufficiently long time to etch the interlayer dielectric film and etching control to stop the etching at thin aluminum electrodes. The variance of the etching rate for interlayer dielectric film often causes short- etching or over-etching of aluminum electrodes, which means electrical connecting through-hole electrodes with aluminum electrodes fail. Therefore, we had not established a high-yield through-hole electrode fabrication process. To realize the high-yield through-hole electrode fabrication in via-last processing, we developed a new electrode structure. In our proposed structure, several internal ´lands´, which share the same area with the external land, are inserted into the interlayer dielectric film just below the external land. The internal lands are formed using the back- end metal layers within the interlayer dielectric film. The propo- sed structure with internal lands is expected to enable the production tolerance and reduce the etching time of the interlayer dielectric film. Our experimental results using a test element group wafer with internal lands reveal that the electrical connecting ratio between the through-hole electrodes and the internal lands was 100% (evaluated with five chips each having 200 connecting points distributed on a 4-inch wafer, which had 166 chips). In addition, the etching time for hole opening decreased by 54% compared with the conventional structure. The high-yield through-hole electrode fabrication enabled us to examine the transistor characteristics using through-hole electrodes. Using through-hole electrodes, 65-nm-node transistors were successfully operated. Additionally, the same transistors were operated even with two chips connected using through-hole electrodes by mechanical caulking. Furthermore, we examined the relationship between the transistor characteristics and the distance from the transistor to the through-hole electrode. In this paper, we focused on the saturation current, which is one of the important characteristics of transistors. The saturation current decreased as the distance from the through-hole electrode became smaller (especially bellow 20 mum).