Performance and design choices of level-two caches

The increasing disparity of speed between processor and its main memory makes ways for multi-level cache hierarchies in almost any of today´s computer systems; specifically, the second-level (L2) caches with larger capacity but longer access time than the first-level (L1) caches have been adopted to reduce this memory gap. In this study an enhanced one-pass trace-driven simulation technique is used to evaluate the design choices of three L2 cache parameters: associativity, line size, and cache size. The traces are from large workloads of both commercial and scientific applications.<>