• DocumentCode
    2068366
  • Title

    A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly

  • Author

    Shengye Wang ; Wei Cao ; Lingli Wang ; Na Wang ; Ping Tao

  • Author_Institution
    State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
  • fYear
    2013
  • fDate
    28-31 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Most of the implementations of boundary scan chains are of fixed length, typically hundreds or thousands. Because the whole chain is scanned every time, many clock cycles are wasted when only a small part of it is concerned. In this paper, a novel structure of configurable boundary scan chain is proposed. Its length and content can be reconfigured without interrupting the chip´s functionality. Experimental result shows that the maximum frequency can be as high as 510.4MHz for a full-configurable chain with 512 cells, under 32 nm process, which is 15.7x better than the intuitive method. The proposed structure has been applied to a processor prototype design, and is expected to meet requirements of different applications.
  • Keywords
    boundary scan testing; integrated circuit design; system-on-chip; clock cycles; configurable boundary scan chain structure; dynamic configurable scan chain bypassing unconcerned segment on the fly structure; processor prototype design; size 32 nm; system on chip; Debugging; Delays; Educational institutions; Multiplexing; System-on-chip; Testing; Boundary Scan Chain; JTAG; Reconfigurable; Segment Tree;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2013 IEEE 10th International Conference on
  • Conference_Location
    Shenzhen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-4673-6415-7
  • Type

    conf

  • DOI
    10.1109/ASICON.2013.6812016
  • Filename
    6812016