New DfT architectures for 3D-SICs with a wireless test port

This paper proposes two Design-for-Test (DfT) architectures for three-dimensional stacked ICs (3D-SICs) with a wireless test port. The two architectures use different test wrappers and TAMs, while the stack is partitioned into two subsets in both schemes. By testing the subsets simultaneously using the wired test port and the wireless test port, considerable test time can be saved. Optimization strategies of the two DfT architectures are discussed, and the total test time is estimated. Experimental results of both proposed optimal DfT architectures show that almost half of the total test time can be saved comparing with that of IEEE p1838 architecture.