Performance estimation of multistreamed, superscalar processors

Multistreamed processors can significantly improve processor throughput by allowing interleaved execution of instructions from multiple instruction streams. We present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Using this technique, estimates of the instructions executed per cycle (IPC) for a processor architecture are quickly calculated given simple descriptions of the workload and hardware characteristics. To validate this technique, estimates of the SPEC89 benchmark suite obtained from the model are compared to results from a hardware simulator. Our results show that the technique produces accurate estimates with an average deviation of /spl sim/4% from the simulation results. Finally, we demonstrate that as the number of functional units increases, multistreaming is an effective technique to exploit these additional resources.<>