Design and implementation of a SoC for privacy storage equipment

Aiming at the issues of slow speed and low security of the removable storage equipment nowadays, this paper proposed a high performance cipher SoC. It integrates an special-designed cipher coprocessor which can realize kinds of cryptographic algorithms. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH)error-correction code (ECC) was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type flash memory. Based on the architecture of Nand Flash Controller, this paper proposed techniques to accelerate the access speed of NAND Flash. The result verified by the development board shows that the proposed SoC can improve the data access performance in both read and program operation of NAND Flash. The built-in coprocessor can support cipher operations with high security, high flexibility and high data throughput.