DocumentCode
2068560
Title
Design and test of an SRAM chip
Author
Wenbin Liu ; Jinhui Wang ; Ligang Hou ; Hongyan Yang ; Jianbo Kang
Author_Institution
VLSI & Syst. Lab., Beijing Univ. of Technol., Beijing, China
fYear
2013
fDate
28-31 Oct. 2013
Firstpage
1
Lastpage
4
Abstract
A fully customized 8×8 bits SRAM chip, based on Chartered 0.35 um EEPROM CMOS technology, is designed and taped-out for low-power and low-cost electronic equipment. According to test results, when the supply voltage is 3.3 V and clock frequency is 20 MHz, the chip can work correctly, and the performance reaches the design specifications, the access time is 6.2 ns and largest power consumption is 6.12 mW.
Keywords
CMOS memory circuits; EPROM; SRAM chips; integrated circuit design; integrated circuit testing; low-power electronics; Chartered EEPROM CMOS technology; SRAM chip design; SRAM chip testing; frequency 20 MHz; low-cost electronic equipment; low-power electronic equipment; size 0.35 mum; time 6.2 ns; voltage 3.3 V; Clocks; Decoding; Layout; Power dissipation; SRAM chips; Vectors; Access time; Chip test; Decoder; SRAM; Sense amplifier;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location
Shenzhen
ISSN
2162-7541
Print_ISBN
978-1-4673-6415-7
Type
conf
DOI
10.1109/ASICON.2013.6812023
Filename
6812023
Link To Document