JEDEC board drop test simulation for wafer level packages (WLPs)

In this paper, a comprehensive study is carried out to investigate the WLP package dynamic behaviors subjected to drop impact according to the JEDEC specification. First, a Direct Acceleration Input (DAI) method, which decouples the board dynamic responses from the test system, thus avoids the difficulties in modeling the complex behaviors of contact between the drop table and drop surfaces, is introduced. The equivalency of the DAI and Input-G methods has been proved mathematically and numerically in this paper. The DAI method removes a rigid-body motion of a test board. Second, the accuracy of global/local modeling techniques is examined in details. Very consistent results were obtained with various distances of cut boundary ranging from 1.5 mm to 3.0 mm for the extended PCB board dimension from the package edge. Third, the dynamic responses of each component on JEDEC board are investigated. It is found that for WLP, the component U1, which is the closest to the mounting hole, will fail first due to the local bending effect. This is different from BGA packages. Such results have been validated by recently reported test data. It is noted that the crack initiation of solder ball always starts at the inner side. The corner balls at each component will fail first compared to the balls in other locations on the same components. The maximum peel stress contours for those critical corner balls at each component map the actual solder ball cracks very well. Fourth, the correlation of the board strain to the solder ball stress is studied with different package sizes with or without underfill. It is observed that board strain at the corner locations of component are not always proportional to the damage exerted on solder balls. Therefore caution must be taken when board strain alone is used to evaluate package dynamic performance. Finally, an improved JEDEC board design is proposed to avoid early failure of corner components by moving the screw locations further away from th- e current specified location. The components at the center column of the modified board will fail first, as observed in many BGA packages. The new board design ensures the package failures come from package intrinsic designs.