Application-specific architectures for field-programmable VLSI technologies

New field-programmable gate array (FPGA) technologies have increased the industrial interest in tools which map a DSP application and a set of performance constraints to a specific VLSI architecture. This paper presents an optimization methodology for mapping a DSP application and a set of performance constraints into an architecture targeted for FPGA technologies with user-programmable RAM blocks on chip. The target architecture supports multiple register files, multiple busses, complex types of functional units, and multichip implementation. The optimization methodology presented in this paper maps DSP applications to optimized register file architectures suitable for FPGAs using a number of different integer programming models. A new integer programming model is presented and used to minimize the number of busses required in the application-specific architectures. Results show that the optimization methodology provides architectures with 22% fewer bus connections than previous research in practical cpu times. For the first time this research provides industry with 1) a high level design optimization methodology that synthesizes application-specific DSP architectures for implementation in new field programmable VLSI technologies, and 2) a methodology to support fast prototyping of DSP applications using multiple FPGA chips.<>