High-aspect ratio copper-via filling for three dimensional chip stacking

Through chip electrodes for three-dimensional packaging can offer the short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing super conformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wave-train. Void-free vias 70 mum in depth and 10 mum in width were formed in 60 minutes using additives in combination with pulse reverse current and dissolved-oxygen enrichment. We further used the micro contact printing method whose top surface of wafer was blocked with self-assembled monolayer of octadecanethiol.