Low jitter clock driver for high-performance pipeline ADC

In order to meet the needs of high-speed high-performance pipeline ADC clock driver, a fast-lock low-jitter 50% duty cycle corrector is designed in 65nm CMOS process in this paper. Both sinusoidal and square external signals can be used as input. The theory of all-digital duty cycle corrector (DCC) is explained. The noise performance of clock buffer is discussed as well. Using 65 nm CMOS process and all-digital structure, simulation results show that with 400MHz sinusoidal input the DCC circuit can produce a clock signal of about 48.72% to 51.3% duty cycle. And the RMS value of jitter for the input buffer is only 45fs. And the locking time only needs 1.5 cycles.