Title :
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC
Author :
Jixuan Xiang ; Jian Mei ; Hao Chang ; Fan Ye
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital-analogue conversion; low-power electronics; CMOS process; FoM; SAR ADC; frequency 186 MHz; power 0.766 mW; preset capacitive DAC; size 65 nm; voltage 1.2 V; word length 8 bit; Capacitors; Clocks; Control systems; Interpolation; Solid state circuits; Timing; Voltage control;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6812049
