A small-area low-power ADC array for image sensor applications

Integrating image sensor and analog-to-digital converter (ADC) array on the same substrate and developing digital image sensor become more and more popular with the development of CMOS technologies. It can reduce the complexity of the whole system and decrease the cost of the system. More importantly, it can integrate more digital signal processing which the traditional image sensor cannot achieve. Integrating ADC array into the image sensor requires ADC to have characters of low power and small area. In this work, a 10-bit is proposed resistor-capacitor hybrid successive approximation register ADC (RC SAR ADC) which uses a resistor ladder to generate 3 reference voltages for last 6 least significant bits (LSB) and shares the shift register of SAR control logic for the ADC array to reduce the area. Theory analysis and simulation show that the proposed RC SAR ADC is suitable for array applications.