DocumentCode :
2069552
Title :
Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologies
Author :
Lele Jiang ; Song Wen ; Wei Tai ; Wang Lei ; Lifu Chang ; Yuhua Cheng
Author_Institution :
Shanghai Res. Inst. of Microelectron. (SHRIME), Peking Univ., Shanghai, China
fYear :
2013
fDate :
28-31 Oct. 2013
Firstpage :
1
Lastpage :
3
Abstract :
In this paper, variations of device parameters, such as threshold voltage (Vth) and saturation current (Idsat), of the devices with and without dog-bone-shaped active-area are investigated with a set of test structures in both 65nm and 40nm CMOS technology processes, respectively. The experiments show that variations of Vth/Idsat of dog-bone devices are more serious than the non-dog-bone device. At 65nm technology node, the inter-die absolute variation of the measured Idsat of dog-bone devices can reach 19.51% while that of standard devices is 11.31%. At 40nm technology node, the inter-die absolute variation of the measured Idsat of dog-bone devices can reach 21.29% while that of non-dog-bone devices is 15.11%. Moreover, the maximum intra-die performance deviation of dog-bone devices from standard devices can be 24% at a 65nm technology and about 42% at a 40nm technology. SPICE simulations show that the device performance variation is mainly due to the channel-width difference caused by photolithography effect. Therefore, it is very important to study both design-for-manufacturability (DFM) and resolution-enhancement-technology (RET) techniques to optimize the design and fabrication of dog-bone devices for IC designs in 65nm and below processes.
Keywords :
CMOS integrated circuits; MOSFET; design for manufacture; photolithography; semiconductor device models; semiconductor device testing; CMOS technology processes; DFM; IC designs; RET techniques; SPICE simulations; design-for-manufacturability; device parameter variations; dog-bone layouts; inter-die absolute variation; maximum intra-die performance deviation; n-MOSFET; non-dog-bone devices; photolithography effect; resolution-enhancement-technology; saturation current; size 40 nm; size 65 nm; threshold voltage; CMOS integrated circuits; CMOS technology; Layout; Lithography; MOSFET; Performance evaluation; Standards; DFM; dog-bone MOSFETs; inter-die variation; intra-die variation; nanometer-scale MOSFET;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
ISSN :
2162-7541
Print_ISBN :
978-1-4673-6415-7
Type :
conf
DOI :
10.1109/ASICON.2013.6812060
Filename :
6812060
Link To Document :
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