Title :
An integrated development environment for reconfigurable operators array
Author :
Shanshan Yong ; Xin´an Wang ; Ying Cao ; Yawei Lu ; Zheng Xie
Author_Institution :
Shenzhen Grad. Sch., Key Lab. of Integrated Micro-Syst. Sci. & Eng. Applic., Peking Univ., Shenzhen, China
Abstract :
In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.
Keywords :
field programmable gate arrays; reconfigurable architectures; FPGA; IDE; ReOps array; architecture file; connection switches; input APU RTL description; integrated development environment; interconnection segments; reconfigurable operator array; Arrays; Educational institutions; Field programmable gate arrays; Hardware design languages; Routing; Wires;
Conference_Titel :
ASIC (ASICON), 2013 IEEE 10th International Conference on
Conference_Location :
Shenzhen
Print_ISBN :
978-1-4673-6415-7
DOI :
10.1109/ASICON.2013.6812061
