Development of on-chip loop coils for evaluation of RF noise suppression film

On-chip planar loop coils with a shielding structure are proposed. The loop size is 100-mum square, and the loop coils are made on a test elementary group (TEG) chip by using 90-nm process technology. The structure consists of a deep-well structure and shielding mesh traces for suppressing on-chip high-frequency noise through the ground on a Si substrate. The magnetic field that causes intra-system interference is measured by the loop coils. We fabricated 3- or 6-mum-thick ferrite thin-film on the TEG chip and evaluated the intra-system interference on the TEG chip using the loop coils. RF noise was applied to the PLL and the I/O circuit, which are standard IP libraries of the Semiconductor Technology Academic Research Center (STARC), using the loop coils. Deformation of the I/O voltage waveform was reduced when ferrite thin-film was fabricated on the TEG chip.