Parallel design verification using standard hardware and sequential software

A novel algorithm for parallel design verification is described. Its data model is that of the data flow computer and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. The significance of this methodology is that, unlike other concepts that cannot use the existing sequential code and can only run on an expensive special-purpose hardware, the proposed approach does not require any code development and can be accommodated by a standard Unix distributed network or a multiprocessor. The author presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network