Distributed VHDL simulation within a workstation cluster

Simulation and verification are very important steps within the development cycle of an integrated circuit. In particular, the simulation of complex architectures in a hardware description language like VHDL is a major time factor within the design process. To accelerate such a simulation, the distribution of the VHDL model database and of the stimuli database within a workstation cluster of general purpose machines has been developed. Compared with other acceleration methods, this distributed simulation method needs no expensive hardware extensions. It uses the temporary idle workstations within a cluster to speed up the simulation. The basics of VHDL and distributed discrete event simulation (DDES) are discussed together with the developed distributed VHDL simulator.<>