Convolution computation on shift switching buses

Presents a novel VLSI architecture for highly parallel computation of the convolution of two vectors of N integers, each consisting of m bits. We adopt a newly proposed switching mechanism that we call ´shift switching´ to achieve a time performance gain. Our algorithm takes total of log N broadcasts, one of them over 15 switches the others over N/2 switches, plus 4 carry-save additions and 2 fast additions. It significantly improves the time performance for the convolution computation for N/spl les/2/sup 7/ and m/spl les/15, while our architecture requires roughly the same amount of hardware as that of an existing highly parallel convolver.<>