Proximity Communication flip-chip package with micron chip-to-chip alignment tolerances

As performance gains from scaling silicon slow, improvements in system performance must come from tighter integration. Proximity communication (PxC) enables designers to aggregate multiple chips that perform as a single large piece of silicon. PxC enables the heterogeneous integration of an optimized mix of process technology and functionality, such as DRAM, flash memory, and CMOS processor chips. PxC enables silicon die placed face-to-face to communicate using close-field capacitive coupling. In a 90 nm standard CMOS technology, using the packaging techniques described in this paper, PxC provides chip-to-chip latency of 2.5 ns at 4 Gb/s per channel with less than 2.5 mW/Gb/s, an areal bandwidth density of over 2 Tb/smm², and a BER less than 10^-18. In this paper, we describe one of our packaging prototypes that enables PxC and provides its system-level benefits.