Design, processing and reliability characterizations of a 3D-WLCSP packaged component

Market demand is increasing for even higher packaging densities, smaller size, lower cost, and more heterogeneous functionality. As a result, three dimensional (3D) packaging has emerged as a leading packaging solution. This paper introduces a 3D Wafer Level CSP packaging architecture that provides a cost effective, rapid time to market alternative to emerging 3D die to wafer integration technologies. Focus is put on the design consideration and processing technologies of the 3D WLCSP including wafer level design rules, wafer level redistribution, wafer bumping, wafer thinning and dicing thinned wafers. The fabrication of test vehicles at the wafer level is discussed. The processing technologies discussed enable the 3D WLCSP with a low package stand off, small package footprint and high package density. Two levels of package interconnections for this 3D WLCSP are presented in this paper. The first level package is qualified by Air to Air Thermal Cycling (AATC) testing with very good reliability performance. The second level assembly shows robust yield on certain package structures. Manufacturing process challenges such as underfill encroachment, lead free CSP reflow profile setting, as well as different underfill methodologies are discussed.