Title :
A high speed memory system based on 16 Mb ST (stretchable memory matrix) DRAMs
Author :
Ooishi, Tsukasa ; Asakura, Mikio ; Hidaka, Hideto ; Arimoto, Kazutami ; Fujishima, Kazuyasu
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A multivalued addressing scheme is proposed for a high-speed, high-packaging-density memory system. A 16-Mb stretchable memory matrix DRAM (16-Mb STDRAM) is examined using this addressing design. This STDRAM with multivalued address signals achieves a 30-ns access time, a high packing density (about 70% of the address for a nonmultiplex type), a power dissipation of 121.5 mA per 80-ns cycle time, and a peak current of 59 mA. The STDRAM has the potential to realize an ultra-low-power memory system
Keywords :
DRAM chips; semiconductor storage; 16 Mbit; 30 ns; 59 mA; DRAMs; STDRAM; access time; cycle time; high speed memory system; multivalued addressing scheme; packing density; peak current; power dissipation; stretchable memory matrix; ultra-low-power memory system; Laboratories; Large scale integration; Microprocessors; Pins; Power dissipation; Random access memory; Research and development; Technological innovation; Timing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
DOI :
10.1109/CICC.1991.164035
