• DocumentCode
    2070725
  • Title

    Do we need wide flits in Networks-on-Chip?

  • Author

    Junghee Lee ; Nicopoulos, C. ; Sung Joo Park ; Swaminathan, Madhavan ; Jongman Kim

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2013
  • fDate
    5-7 Aug. 2013
  • Firstpage
    2
  • Lastpage
    7
  • Abstract
    Packet-based Networks-on-Chip (NoC) have emerged as the most viable candidates for the interconnect backbone of future Chip Multi-Processors (CMP). The flit size (or width) is one of the fundamental design parameters within a NoC router, which affects both the performance and the cost of the network. Most studies pertaining to the NoC of general-purpose microprocessors adopt a certain flit width without any reasoning or explanation. In fact, it is not easy to pinpoint an optimal flit size, because the flit size is intricately intertwined with various aspects of the system. This paper aims to provide a guideline on how to choose an appropriate flit width. It will be demonstrated that arbitrarily choosing a flit width without proper investigation may have serious repercussions on the overall behavior of the system.
  • Keywords
    logic design; microprocessor chips; network routing; network-on-chip; NoC router; chip multiprocessors; flit width; general purpose microprocessors; networks-on-chip; optimal flit size; Equations; Ports (Computers); Power demand; Switches; Throughput; Wires; Wiring; Flit Size/Width; Link Width Optimization; Network-on-Chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Natal
  • ISSN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2013.6654614
  • Filename
    6654614