Searching for the worst-case eye diagram of a signal channel in electronic packaging system including the effects of the nonlinear I/O devices and the crosstalk from adjacent channels

In this paper, we propose a new method for the prediction of the worst case eye diagram for the high performance chip to chip interconnections utilizing SERDES I/O. This method employs transient circuit simulations using an adequate length of all possible bit patterns at the input of driver, so that the worst-case eye at the receiver input can be determined. The signal channels are modeled with multi-port S-parameters. The Mpilog macromodels are used for the I/O devices modeling accurately the nonlinear properties of these devices. The peaks of the crosstalk from adjacent channels are aligned to the worst-case single channel eye diagram for several worst-case scenarios to produce the absolute worst-case eye diagram. The proposed method was applied to the SERDES interconnections of a high-end computer and yielded accurate worst-case eye diagram results with acceptable simulation speed.