Slot crossing and non-native IO voltage referencing: Effectiveness of image return capacitance to address signal integrity concerns

There is a growing requirement to thoroughly understand the tradeoffs made in "real-world" applications where package cross sections provide insufficient planes for both desirable IO referencing and DC current delivery. Allowing minimal split crossings and using significant decoupling are widely known design-guide "solutions". It is also well known that slot crossing within any high-speed application should be avoided. This paper will perform a real-world study of current return paths on various carrier referencing structures and quantify, in terms of margin degradation, how concerning slot crossings really are and what can be done to mitigate these losses. This paper will not perform a "text-book" study of slot crossing phenomena; rather it will quantify signal integrity tradeoffs in modern, cross-section challenged, high-speed applications. This paper will discuss IO referencing, signal integrity, power distribution, decoupling, and cross-section trade-offs within an exemplary system including a high-speed memory application. Analysis will use a real-world example to quantify conventional implementation compromises and how each trade-off impacts performance, cost, design risk, and breaking points. Specifically, this paper will discuss and quantify: 1) The effect of interrupted reference planes on high-speed IO as frequency and the number of simultaneous switches varies 2) Margin degradation due to insufficient cross-sections creating mismatched driver IO and implemented reference voltages 3) Effectiveness of image return capacitors against IO referencing VCC that is not native to their driver supply.