Ground gated 8T SRAM cells with enhanced read and hold data stability

Author

Hailong Jiao ; Kursun, V.

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2013

fDate

5-7 Aug. 2013

Firstpage

52

Lastpage

57

Abstract

A new asymmetrically ground-gated eight-transistor (8T) static random access memory (SRAM) circuit with enhanced data stability characteristics is proposed in this paper. A robust and low leakage SLEEP mode with data retention capability is provided by utilizing asymmetrical ground gating in an idle memory array. The data stability is enhanced by 2.22× and 53.54% during read operations and data retention SLEEP mode, respectively, with the proposed asymmetrically ground-gated 8T memory circuit as compared to a conventional ground-gated six-transistor (6T) SRAM cell in a TSMC 65nm CMOS technology. The overall electrical quality is also enhanced by 2.84× with the proposed asymmetrically ground-gated 8T SRAM circuit as compared to the conventional ground-gated 6T memory array.

Keywords

CMOS memory circuits; SRAM chips; TSMC CMOS technology; asymmetrical ground gating; asymmetrically ground-gated eight-transistor static random access memory circuit; data retention SLEEP mode; data retention capability; electrical quality; enhanced read and hold data stability; ground gated 8T SRAM Cells; leakage SLEEP mode; memory array; Arrays; Circuit stability; Memory management; Power demand; SRAM cells; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on

Conference_Location

Natal

ISSN

2159-3469

Type

conf

DOI

10.1109/ISVLSI.2013.6654622

Filename

6654622