Title :
On the selection of efficient arithmetic additive test pattern generators [logic test]
Author :
Manich, S. ; Garcia, L. ; Balado, L. ; Lupon, E. ; Rius, J. ; Rodriguez, R. ; Figueras, J.
Author_Institution :
Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) which allow the excitation and observation of potential faults in the circuit. Arithmetic additive TPGs (AdTPG) allow existing internal datapaths to be reused to perform this operation without a penalty in the circuit area. AdTPGs are configured by means of triplets: a combination of seed, increment and number of times the increment is added to the seed. Since the selection of triplets is crucial to the quality of the test vectors obtained and the test resources used, an emerging research interested in the topic is observed. In this paper, a method for generating efficient triplets which enable a reduction of memory requirements and test application time for a given fault coverage (FC) level is presented.
Keywords :
automatic test pattern generation; built-in self test; digital arithmetic; logic testing; AdTPG; BIST; TPG; arithmetic additive test pattern generators; built-in self test; fault coverage level; incremental addition; internal datapath reuse; seed; test vector quality; triplets selection; Additives; Arithmetic; Automatic test equipment; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Greedy algorithms; Random number generation; Test pattern generators;
Conference_Titel :
Test Workshop, 2003. Proceedings. The Eighth IEEE European
Print_ISBN :
0-7695-1908-3
DOI :
10.1109/ETW.2003.1231662
