Scan test strategy for asynchronous-synchronous interfaces [SoC testing]

In the next few years, the well-known synchronous design style will not be able to keep pace with the increase of speed and capabilities of integration of advanced processes. Asynchronous design will become more and more common among digital designs, while synchronous-asynchronous interactions will emerge as a key issue in future SoC designs. This paper presents test strategies for 2-phase asynchronous-synchronous, and vice versa, interfaces. It is shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors are able to test all the stuck-at-faults within the asynchronous-synchronous interfaces.