Jitter suppressed on-chip clock distribution using package plane cavity resonance

This paper presents a chip-package hybrid clock distribution network using package or PCB plane cavity resonance. This structure enhances Q factor through low loss plane cavity and lowers phase noise. A voltage-controlled oscillator generates clock signal and off-chip driver circuit with the structure of harmonic rejection mixer excites the plane resonance. The plane cavity resonator consists of the embedded planes in package and an inductive load. The resonant frequency can be controlled by the inductance and the various destination points like local buffers can be connected to the plane. We simulate the proposed chip-package co-design with the transmission line matrix modelling and the simulation results show that the source jitter is suppressed by the resonance effect.