DocumentCode
2071381
Title
Topological fault simulation method
Author
Hahanov, Vladimir ; Melnikova, Olga ; Zaychenko, Sergey ; Guz, Olesya
Author_Institution
APVT Dept., Kharkov Nat. Univ. of Radioelectron., Ukraine
fYear
2004
fDate
28-28 Feb. 2004
Firstpage
602
Lastpage
605
Abstract
The superposition procedure modification - topological fault simulation method is offered. It lies in backtracing of defects on topology of the circuit. It is oriented on gate-level description of the circuits. According to it, the set of reconvergent fan-outs and tree-like structures are being defined in the description of the device.
Keywords
fault simulation; network topology; trees (mathematics); circuit topology; defect backtracing; gate level description; reconvergent fan outs; superposition procedure modification; topological fault simulation; tree like structures; Algorithm design and analysis; Application specific integrated circuits; Circuit faults; Circuit simulation; Circuit testing; Circuit topology; Digital systems; Electrical fault detection; Fault detection; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Modern Problems of Radio Engineering, Telecommunications and Computer Science, 2004. Proceedings of the International Conference
Conference_Location
Lviv-Slavsko, Ukraine
Print_ISBN
966-553-380-0
Type
conf
Filename
1366087
Link To Document