Title :
Code generation for functional validation of pipelined microprocessors
Author :
Corno, F. ; Squillero, G. ; Sonza Reorda, M.
Author_Institution :
Dipt. di Automatica e Informatica, Politecnico di Torino, Italy
Abstract :
Functional verification of pipelined microprocessors is a challenging task, as the behavior of a pipeline is determined by a sequence of instructions and by the interaction between their operands. This paper describes an approach to test-program generation based on an evolutionary algorithm. The proposed methodology is able to tackle complex pipelined designs. Human intervention is limited to the enumeration of all assembly instructions, and also internal parameters of the optimizer are auto-adapted. A prototype was built and exploited to generate test programs for the DLX/pII, a simple pipelined microprocessor. Test programs were devised, trying to maximize the RT-level statement coverage. Results show the feasibility and effectiveness of the method.
Keywords :
evolutionary computation; integrated circuit testing; logic simulation; logic testing; microprocessor chips; pipeline processing; RT-level statement coverage; assembly instructions; auto-adapting optimizer; evolutionary algorithm; instruction sequences; microprocessor design validation; microprocessor functional validation; microprocessor test code generation; pipelined microprocessor; test-program generation; verification; Conferences; Microprocessors; Testing;
Conference_Titel :
Test Workshop, 2003. Proceedings. The Eighth IEEE European
Print_ISBN :
0-7695-1908-3
DOI :
10.1109/ETW.2003.1231677