DocumentCode :
2071580
Title :
High performance self-checking adder for VLSI processor
Author :
Shih, F. Warren
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
1991
fDate :
12-15 May 1991
Abstract :
The author describes a novel carry select adder design which has high performance and is self-checking without requiring a large amount of circuit overhead. A CMOS implementation of the adder is shown to comply with critical requirements of a VLSI processor. Simulation results show that the self-checking adder can easily satisfy the clock requirements of a VLSI processor. The circuit area overhead of the self-checking design is only 13% of the total adder area, which is considerably lower than that of some parity prediction checking schemes that require almost a 100% circuit overhead
Keywords :
CMOS integrated circuits; VLSI; adders; digital arithmetic; fault tolerant computing; microprocessor chips; CMOS; VLSI processor; carry select adder design; circuit area overhead; circuit overhead; high performance; self-checking; self-checking adder; Adders; CMOS logic circuits; CMOS process; Circuit faults; Clocks; Multiplexing; Propagation delay; Signal design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0015-7
Type :
conf
DOI :
10.1109/CICC.1991.164039
Filename :
164039
Link To Document :
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