High density and high performance ECL: some design tips

Author

Lyon, Terry L.

Author_Institution

Control Data Corp., Arden Hills, MN, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

38721

Abstract

Recent developments in ECL (emitter-coupled logic) circuit technology have led to a new generation of high-density and higher-performance gate arrays. The choice of an ECL ASIC (application-specific integrated circuit) technology is discussed with regard to the use of proven versus new technology, ASIC benchmarks, and second sourcing. Design issues considered are the optimization of density and performance, power limits, estimated versus actual interconnect delays, pulse shrinkage and clocking, packaging, and cooling

Keywords

VLSI; application specific integrated circuits; bipolar integrated circuits; cooling; emitter-coupled logic; integrated circuit technology; logic arrays; packaging; ASIC benchmarks; ECL ASIC; ECL circuit technology; ECL gate arrays; application-specific integrated circuit; clocking; cooling; design tips; emitter-coupled logic; high density ECL; high performance ECL; interconnect delays; new generation; optimization of density; packaging; power limits; pulse shrinkage; second sourcing; Application specific integrated circuits; Clocks; Cooling; Delay estimation; Design optimization; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Logic arrays; Logic circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123168

Filename

123168