Title :
Design of a Low Noise Amplifier with integrated antenna for 60 GHz wireless communications
Author :
Fonte, A. ; Saponara, S. ; Pinto, G. ; Fanucci, L. ; Neri, B.
Author_Institution :
Dipt. di Ing. dell´´Inf., Univ. di Pisa, Pisa, Italy
Abstract :
The integration of a Low Noise Amplifier (LNA) with on-chip antenna for 60 GHz short-range wireless applications is discussed in the paper. A 65 nm CMOS Silicon-on-Insulator (SOI) technology has been selected as target. With respect to the state of the art, the on-chip co-design of LNA and antenna permits avoiding a pre-defined constraint of 50 Ohm impedance matching. By relaxing the impedance matching specification a LNA with only two amplification stages has been designed to reach the desired power gain (>;20 dB) and noise figure (<; 5 dB) with a power consumption and circuit complexity optimized vs. state-of-art LNAs with similar performances. A dipole antenna with coplanar strip feed has been also designed matching the 20 Ohm input LNA impedance and allowing an extra gain of 3 dB at 60 GHz with a limited on-chip area occupation.
Keywords :
CMOS analogue integrated circuits; coplanar waveguides; impedance matching; low noise amplifiers; millimetre wave antennas; radiocommunication; silicon-on-insulator; CMOS silicon-on-insulator technology; LNA; SOI technology; circuit complexity; coplanar strip feed; frequency 60 GHz; gain 3 dB; impedance matching; integrated antenna; low noise amplifier; power consumption; resistance 50 ohm; size 65 nm; wireless communications; CMOS integrated circuits; CMOS technology; Dipole antennas; Gain; System-on-a-chip; Wireless communication; 60-GHz; CMOS Silicon On Insulator (SOI); LNA (low-noise amplifier); On-chip antenna; Wireless Gbits/s;
Conference_Titel :
Microwave Workshop Series on Millimeter Wave Integration Technologies (IMWS), 2011 IEEE MTT-S International
Conference_Location :
Sitges
Print_ISBN :
978-1-61284-963-8
DOI :
10.1109/IMWS3.2011.6061864
