• DocumentCode
    2071682
  • Title

    Design of standard-cell libraries for asynchronous circuits with the ASCEnD flow

  • Author

    Trevisan Moreira, Matheus ; Vilar Calazans, Ney Laert

  • Author_Institution
    GAPH - Fac. of Inf., Pontifical Catholic Univ. of Rio Grande do Sul, Porto Alegre, Brazil
  • fYear
    2013
  • fDate
    5-7 Aug. 2013
  • Firstpage
    217
  • Lastpage
    218
  • Abstract
    This work presents the ASCEnD flow, a design flow devised for the design of components required for the design of asynchronous systems using standard-cells. The flow is fully automated except for the layout generation step, and can be parameterized for any CMOS technology. It was employed in the design of a dedicated standard-cell library, which contains over five hundred components, for the STMicroelectronics 65 nm technology. This library supported implementation of different circuits, like network-on-chip routers and cryptographic cores.
  • Keywords
    CMOS integrated circuits; network-on-chip; ASCEnD flow; CMOS technology; STMicroelectronics technology; asynchronous circuits; asynchronous systems; cryptographic cores; design flow; layout generation step; network on chip routers; standard cell libraries; Asynchronous circuits; Inverters; Layout; Libraries; Logic gates; Standards; Transistors; asynchronous; design flow; standard-cell;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Natal
  • ISSN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2013.6654647
  • Filename
    6654647