DocumentCode :
2071692
Title :
Optimization of chemistry and process parameters for void-free copper electroplating of high aspect ratio through-silicon vias for 3D integration
Author :
Malta, Dean ; Gregory, Christopher ; Temple, Dorota ; Wang, Chen ; Richardson, Thomas ; Zhang, Yun
Author_Institution :
RTI Int., Research Triangle Park, NC
fYear :
2009
fDate :
26-29 May 2009
Firstpage :
1301
Lastpage :
1306
Abstract :
The through-silicon via is a key element in the development of 3D integration technology for new generations of advanced electronic systems. There are several challenges associated with filling these deep, relatively large diameter vias using standard copper electroplating processes, like those common in damascene technology. This paper will summarize a process development for copper electroplating of deep silicon vias in the range of 20-200 mum in diameter and 150-375 mum in depth. The test vias had aspect ratios ranging from 1.3:1 to 8:1, with sidewalls which were approximately vertical. The paper will discuss copper via plating results with respect to additive component levels, current density, seed layer quality, and sample pretreatments pertaining to wetting of the vias in the plating solution.
Keywords :
electroplating; silicon; 3D integration technology; advanced electronic systems; chemistry; high aspect ratio; process parameters; through-silicon vias; void free copper electroplating; Additives; Chemical elements; Chemical technology; Chemistry; Copper; Current density; Filling; Silicon; Testing; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
978-1-4244-4475-5
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2009.5074179
Filename :
5074179
Link To Document :
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