• DocumentCode
    2071920
  • Title

    A novel optimization method for reversible logic circuit minimization

  • Author

    Morrison, Matthew ; Ranganathan, Nagarajan

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    2013
  • fDate
    5-7 Aug. 2013
  • Firstpage
    182
  • Lastpage
    187
  • Abstract
    Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. We present an optimization method for reversible logic synthesis based on the Integrated Qubit (IQ) library. This method works in conjunction with existing methods to further improve quantum cost and delay of a synthesized reversible logic circuit. This algorithm runs in O(N) time, and reduces the quantum cost of synthesized circuit by up to 45 percent. In addition, the process of replacing the gates in the synthesized circuits with IQ gates uses a locally optimal technique whose major benefits include reduction of cost as well as delay.
  • Keywords
    logic circuits; logic design; nanotechnology; optimisation; programmable logic devices; quantum computing; IQ gates; arithmetic logic unit designs; circuit heat generation; integrated qubit library; logic design; nanotechnology; optimization method; programmable reversible logic; quantum computer algorithms; quantum computing; reversible logic circuit minimization; reversible logic synthesis; synthesized circuits; Algorithm design and analysis; Delays; Libraries; Logic gates; Minimization; Quantum computing; Sequential analysis; Integrated Qubits; Quantum Computing; Reversible Logic; Sequencing Graphs; Synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Natal
  • ISSN
    2159-3469
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2013.6654656
  • Filename
    6654656