Neutron-induced single event effects analysis in a SAR-ADC architecture embedded in a mixed-signal SoC

This paper describes a neutron-induced single event effect test in analog-to-digital converters of a Microsemi´s programmable commercial mixed-signal system-on-chip. The main objective is to investigate the reliability of the charge redistribution successive approximation register architecture of the analog-to-digital converters (SAR-ADC) embedded into this device, considering critical application projects. The case-study circuit is a data acquisition system that uses the two available analog-to-digital converters (ADCs), being one converter controlled by the embedded processor and the other by the digital programmable matrix of the device. This scheme is based on a design diversity redundancy concept. The setup was exposed to a neutron source at the CCLRC Rutherford Appleton Laboratory - ISIS in order to investigate the occurrence of SEEs ranging from single to errors bursts. Also, SPICE simulations were carried out in a charge redistribution SAR-ADC architecture in order to clarify the results obtained from this experiment.