Title :
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores
Author :
Nagarajan, Vijay ; Lakshminarasimhan, Kartik ; Sridhar, Arvind ; Thinakaran, Prashanth ; Hariharan, R. ; Srinivasan, V. ; Kannan, Ram Srivatsa ; Sridharan, Arun
Abstract :
Future generation supercomputing clusters are endeavouring to achieve exascale performance without compromise on energy efficiency. Executing multiple applications simultaneously without space time sharing in a heterogeneous multi core environment brings out the utmost parallelism that exists within the applications. This helps to attain peak performance and also paves way for improved resource utilization. This necessitates the need for an efficient and locality aware cache replacement scheme to cater to the magnanimous data needs of underlying functional units in case of a cache miss. Reduced cache miss improves resource utilization and reduces data movement across the core which in turn contributes to a high performance to power ratio. This paper proposes a novel application aware cache replacement policy in which data blocks are assigned weights based on a set of application and data statuses. Our proposed heuristics have shown an 8-11% improvement in cache hit when compared against conventional cache replacement heuristics.
Keywords :
cache storage; logic design; cache replacement heuristics; cache system design; heterogeneous cores; locality aware cache replacement scheme; reduced cache miss; resource utilization; Computational modeling; Computer architecture; Hardware; Organizations; Resource management; Silicon; System analysis and design; Cache System Design; Multiple Application Execution; Replacement Policy;
Conference_Titel :
VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on
Conference_Location :
Natal
DOI :
10.1109/ISVLSI.2013.6654659